The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a method for the preparation of a single crystal silicon wafer. This wafer comprises a surface having an epitaxial silicon layer deposited thereon, and forms an ideal, non-uniform depth distribution of oxygen precipitates during the heat treatment cycles of essentially any electronic device manufacturing process.
Single crystal silicon, which is the starting material for most processes used to fabricate semiconductor electronic components, is commonly prepared by using the Czochralski (xe2x80x9cCzxe2x80x9d) process. In this method, polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) is charged to a crucible and melted, a seed crystal is brought into contact with the molten silicon, and a single crystal ingot is grown by slow extraction.
During the Cz process, defects can form in the single crystal silicon as the crystal cools after solidification. One particularly problematic type of defect is the presence of voids within the body of the ingot. The source these voids is believed to be the agglomeration of silicon lattice vacancies. Typically, the voids (or xe2x80x9cvacancy agglomeratesxe2x80x9d) have an octahedral shape and a characteristic size of at least about 0.01 xcexcm. When the ingot is sliced into wafers, these vacancy agglomerates are exposed and appear as pits on the surfaces of the wafers. These pits (referred to as xe2x80x9ccrystal originated pitsxe2x80x9d or xe2x80x9cCOPsxe2x80x9d), in turn, interfere with the performance of the wafer.
To date, there are three main approaches to reducing the number density of COPs. The first approach focuses on crystal pulling techniques to reduce the number density of vacancy agglomerates within the ingot. For example, it has been suggested that the number density of such vacancy agglomerates can be reduced by controlling v/G0 (wherein v is the growth velocity and G0 is the average axial temperature gradient) to grow a crystal in which crystal lattice vacancies (as opposed to self-interstitials) are the dominant intrinsic point defect, and then influencing the vacancy agglomerate nucleation rate by altering (generally, by slowing down) the cooling rate of the silicon ingot from 1100xc2x0 C. to 1050xc2x0 C. during the crystal pulling process. While such a method reduces the number density of vacancy agglomerates, it does not prevent their formation. Another crystal pulling method for reducing the number density of vacancy agglomerates involves reducing the pull rate to a value less than 0.4 mm/minute. This method, however, also is not satisfactory because such a slow pull rate leads to reduced throughput for each crystal puller. And more importantly, such a pull rate leads to the formation of single crystal silicon having a high concentration of self-interstitials. This high concentration, in turn, leads to the formation of self-interstitial agglomerates, which also are problematic.
A second approach which has been used to reduce the number density of COPs focuses on the dissolution or annihilation of the vacancy agglomerates subsequent to their formation. Generally, this is achieved by using high-temperature heat treatments of the silicon in wafer form. For example, in European Patent Application No. 503,816 A1, Fusegawa et al. propose growing the silicon ingot at a growth rate in excess of 0.8 mm/minute, and heat treating the wafers which are sliced from the ingot at a temperature in the range of 1150xc2x0 C. to 1280xc2x0 C. to reduce the vacancy agglomerate density in a thin region near the wafer surface. This approach is disadvantageous because it provides no uniform procedure. The specific treatment needed varies depending on the concentration and location of the vacancy agglomerates in the wafer. In fact, different wafers cut from an ingot which does not have a uniform axial concentration of such agglomerates may require different processing conditions. Further, the heat treatments of this approach are relatively costly, and have the potential for introducing metallic impurities into the wafers.
A third approach to dealing with the problem of COPs is the epitaxial deposition of a thin crystalline layer of silicon onto the surface of the wafer. This process provides a wafer having a surface which is substantially free of COPs. Use of the traditional epitaxial deposition techniques, however, substantially increases the cost of the wafer.
In addition to containing the above-discussed vacancy agglomerates, single crystal silicon prepared by the Cz method also typically contains various impurities, among which is mainly oxygen. This contamination occurs, for example, while the molten silicon is contained in the quartz crucible. At the temperature of the silicon molten mass, oxygen comes into the crystal lattice until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in solidified silicon. Such concentrations are greater than the solubility of oxygen in solid silicon. Thus, as the crystal grows from the molten mass and cools, the solubility of oxygen in it decreases rapidly. This ultimately results in wafers containing oxygen in supersaturated concentrations.
When a wafer contains a supersaturated concentration of oxygen, heating the wafer (such as during a typical thermal treatment used during the fabrication of an electronic device) can cause the oxygen to precipitate within the wafer. The oxygen precipitates can be either harmful or beneficial, depending on their location. Oxygen precipitates located in the active device region of the wafer (i.e., typically near the surface) can impair the operation of the device. On the other hand, oxygen precipitates located in the bulk of the wafer tend to be beneficial because they are capable of trapping undesired metal impurities that may come into contact with the wafer. The use of oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to as internal or intrinsic gettering (xe2x80x9cIGxe2x80x9d).
Historically, electronic device fabrication processes have included a series of steps which were designed to produce silicon having a region near the surface of the wafer which is free of oxygen precipitates (commonly referred to as a xe2x80x9cdenuded zonexe2x80x9d or a xe2x80x9cprecipitate-free zonexe2x80x9d) with the balance of the wafer (i.e., the wafer bulk) containing a sufficient number of oxygen precipitates for IG purposes. Such oxygen precipitation profiles have been formed, for example, in a high-low-high thermal sequence such as (a) oxygen out-diffusion heat treatment at a high temperature ( greater than 1100xc2x0 C.) in an inert gas for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600 to 750xc2x0 C.), and (c) growth of oxygen (SiO2) precipitates at a high temperature (1000 to 1150xc2x0 C.). See, e.g., F. Shimura, Semiconductor Silicon Crystal Technology, pp. 361-367 (Academic Press, Inc., San Diego Calif., 1989) (and the references cited therein).
More recently, however, advanced electronic device manufacturing processes, such as DRAM manufacturing processes, have begun to minimize the use of high-temperature process steps. Although some of these processes retain enough of the high-temperature process steps to produce a denuded zone and sufficient density of bulk precipitates, the tolerances on the material are too tight to render it a commercially viable product. Other current highly advanced electronic device manufacturing processes contain no out-diffusion steps at all. Because of the problems associated with oxygen precipitates in the active device region, therefore, these electronic device fabricators generally must use silicon wafers which are incapable of forming oxygen precipitates anywhere in the wafer under their process conditions. As a result, IG potential is lost.
The present invention provides for a process for preparing a single crystal silicon wafer which (a) has a surface that is essentially free of COPs; and (b) forms an ideal, non-uniform depth distribution of oxygen precipitates during a heat treatment cycle of essentially any electronic device manufacturing process. This process may advantageously be used with, for example, a wafer starting material which has an oxygen concentration of no greater than about 18 ppma.
Briefly, therefore, this invention is directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon. In one embodiment, an epitaxial layer is deposited onto a surface of a silicon wafer. The wafer is also heated to a temperature of at least about 1175xc2x0 C. This heat treatment begins either during or after the epitaxial deposition. Following the heat treatment, the heated wafer is cooled for a period of time at a rate of at least about 10xc2x0 C./sec while (a) the temperature of the wafer is greater than about 1000xc2x0 C., and (b) the wafer is not in contact with a susceptor. In this process, the epitaxial deposition, heating, and cooling are conducted in the same reactor chamber.
In another embodiment, an epitaxial layer is deposited onto a wafer surface which has an average light scattering event concentration of at least about 0.5/cm2, as measured by a laser-based auto inspection tool configured to detect light scattering events corresponding to polystyrene spheres having diameters of no less than about 0.12 xcexcm. The wafer is also heated to a temperature of at least about 1175xc2x0 C. This heat treatment begins either during or after the epitaxial deposition. Following the heat treatment, the wafer is cooled at a rate of at least about 10xc2x0 C./sec for a period of time while the temperature of the wafer is greater than about 1000xc2x0 C. In this process, the epitaxial deposition, heating, and cooling are conducted in the same reactor chamber.
In a further embodiment, an epitaxial layer having a thickness of at least about 0.1 and less than 3 xcexcm is deposited onto a surface of a silicon wafer. The wafer is also heated to a temperature of at least about 1175xc2x0 C. This heat treatment begins either during or after the epitaxial deposition. Following the heat treatment, the wafer is cooled at a rate of at least about 10xc2x0 C./sec for a period of time while the temperature of the wafer is greater than about 1000xc2x0 C. In this process, the epitaxial deposition, heating, and cooling are conducted in the same reactor chamber.
Other features of this invention will be in part apparent and in part pointed out hereinafter.